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The latest Electronics Weekly product news involving software, such as Linux, MathWorks and PCB designers.

Google begins roll out of Android 15, available at AOSP

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Google has begun the process of rolling out Android 15, the latest version of its mobile operating system, beginning with Pixel devices. Specifically, the company has released the Android 15 source code and made it available at the Android Open Source Project (AOSP). While the latest major release will be available on supported Pixel devices in “coming weeks”, access will ...

Google rebrands TensorFlow Lite to LiteRT

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Google is rebranding TensorFlow Lite to LiteRT (as in “lite runtime”). This lets you deploy ML and AI models on Android, iOS, and embedded devices. Basically, for on-device AI at the Edge. Google writes about the name change for the runtime that supports models other than those solely authored with TensorFlow: “Since its debut in 2017, TFLite has enabled developers ...

Scope-like data visualisation for Segger SystemView

Segger SystemView DataPlot

Segger has added an oscilloscope-like window to its SystemView embedded system analysis software to record variable data alongside runtime events. Called DataPlot, its graphs are synchronised with SystemView’s Timeline and CPU Load windows. Data can be sent in fixed point or floating-point formats and multiple variables can be recorded – each identifiable by a descriptive name and a different color ...

Nvidia offers blueprints from which to develop generative AI applications

Nvidia blueprints

Nvidia has announced pre-trained, customisable AI workflows for creating customer service avatars, for data-mining pdf documents, and for virtual drug screening. They are the first three ‘NIM Agent Blueprints’, which the company said will be a catalogue of products to jump-start developers creating applications based on AI agents. They include sample applications built with Nvidia’s ‘NeMo’, ‘NIM’ and partner micro-services, ...

Siemens adds AI to simulation tools

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The increased complexity of semiconductor designs that need validating is a problem for simulators, says Pradeep Thiagarajan, principal product manager for custom IC verification, introducing Siemens’ Solido Simulation Suite software (Solido Sim). The suite has three new simulators: Solido SPICE, Solido Fast SPICE and Solido LibSPICE software, together with the company’s AFS platform, ELDO software and Symphony software. Solido Sim ...

Autosar tool trial for Infineon TC4x automotive processors

HighTec Infineon TC4x MCAL eval

HighTec EDV-Systeme has announced a time-limited evaluation bundle for Autosar-based development using Infineon’s TC4x automotive processors, created with Infineon. In Autosar development, besides a run-time environment and an application layer, ‘basic software’ is needed – which consists of pre-defined modules that are summarised in layers. The layers are intended to make it easier to migrate software to different hardware. One of these ...

Altair to acquire Metrics Design Automation

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At DAC 2024, Altair showcased its 3D-IC design and SimLab multi-physics modelling and simulation tool. Today, the company has announced the acquisition of Metrics Design Automation, a Canadian company led by Joe Costello , former CEO of Cadence Design Systems (1988-1997). The company described DSim as a full feature System Verilog and VHDL RTL simulator. It enables designers to simulate ...

Accellera announces Federated Simulation Standard working group

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DAC 2024: Accellera Systems Initiative, the EDA standards body, reflects the industry’s shift of focus from chip to systems, with the formation of a new working group. The Federated Simulation Standard (FSS) working group will focus on the Interoperability of simulators, models, and other components that together form systems-of-systems simulation environments, said Martin Barnasconi, Accellera’s technical committee chair and chair ...

NoC design tool is cloud-based

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DAC 2024: Believed to be the first cloud-based NoC (network on chip) design tool, the iNoCulator is available on an early access basis from SignatureIP. Today, there is a need to design multiple chipets and design scalable designs with chiplet-based systems, explained Purna Mohanty, CEO of SignatureIP. As the interconnect between compute, storage, memory and I/O blocks on a chip, ...

Focus shifts for HDL workflow in chiplet era

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DAC 2024: The need to organise HDL hardware description language) tools in an era of chiplet design and higher abstraction and higher synthesis levels, Sigasi has introduced its Visual HDL portfolio, designed to correct inefficient HDL-based design workflows and reduce the number of iterations needed. The Belgium company explained that SVH (Sigasi Visual HDL) is an IDE (integrated development environment) ...