Focus shifts for HDL workflow in chiplet era

DAC 2024: The need to organise HDL hardware description language) tools in an era of chiplet design and higher abstraction and higher synthesis levels, Sigasi has introduced its Visual HDL portfolio, designed to correct inefficient HDL-based design workflows and reduce the number of iterations needed.

The Belgium company explained that SVH (Sigasi Visual HDL) is an IDE (integrated development environment) which supports the shift-left methodology for chip design (ie., moving tasks to earlier in the design process) to catch specification errors early and fix the inefficient HDL-based design flow.

This approach improves the traditional HDL-based design and verification flow, commented CEO Dieter Therssen, “enabling [hardware designers and verification engineers] . . . to create, integrate, and validate their designs while leveraging shift-left principles.”


The advent of generative AI and complex SoC IP means that design specifications have increased, requiring new levels of abstraction to plug and play alongside large HDL files which contain functionality created with domain-specific knowledge in order to integrate hundreds of billions of transistors on a chip.


SVH validates code early in the design flow, before simulation and synthesis flows by standardising the concept of an HDL design project, moving simulation and synthesis projects into an IDE, synchronous visualisation and earlier validation.

SVH is fully integrated with Microsoft’s Visual Studio Code (VS Code), and includes applications to use git and GitHub Source Control Management, as well as a selection of utilities to facilitate mundane tasks, such as extracting ‘to-do’comments or bookmarking important sections in HDL code.

Users move seamlessly through hierarchy views and graphics that update instantaneously as they make changes in their code. It alerts the user to problems as they enter HDL code, enforcing coding styles from syntax and semantics, to enforcing coding styles to meet safety standards (e.g., DO-254 or ISO 26262) and also flags up UVM abuses.

Dirk Seynhaeve, Sigasi’s VP business development, said that customers are reporting 10-30% gains in productivity.

There are three commercial editions to meet specific SoC design and verification challenges and seamless integration with an AI engine. Designer Edition includes all the essential guidelines and tools to create quality code: from hovers and autocompletes to quick fixes, formatting, and rename refactoring, Professional Edition adds more complex features focused on verifying HDL specifications, e.g., graphic features, and UVM support. Enterprise Edition is for large engineering teams, and includes command-line interface capabilities to safeguard the code repository and ensure better handoff to verification groups. It also includes documentation generation, all part of a better HDL hand-off.

The Community Edition is the default option. It lets users explore its features for non-commercial uses. Students and teachers can download the VS Code extension and upgrade their HDL education.


Leave a Reply

Your email address will not be published. Required fields are marked *

*