300GHz receiver with 300GHz silicon transistors

According to the thesis of Sumit Singh, studying at University of Oulu in Finland, down-conversion of the 300GHz carrier is initially by a local oscillator at two-thirds of the carrier, then by I and Q signals at one-third of the carrier.

“Consequently, this architecture reduces power consumption, I/Q imbalances, and added phase noise and mixing-spurs caused by the long multiplier chain in the local oscillator signal generation,” according to Singh in the thesis. “Additionally, sliding-IF architecture facilitates signal amplification at the IF stage, which also reduces the noise contribution of the subsequent I/Q mixing stage.”

Power consumption is under 400mW and maximum conversion gain is 15.2dB at 310GHz. Measurements show a -17dBm input-referred compression point, and a single side-band noise figure of 29.5dB.

Error vector magnitude is 8.2% for 16QAM with 4GHz namdwidth, 5.5% with 64QAM 2GHz and 2.7% with 256QAM 500KHz.

To increase signal-to-noise ratio, Singh also implemented am LNA (low-noise amplifier) – a multistage pseudo-differential cascode with 12.9dB gain, 23GHz 3dB bandwidth, and a 16dB noise figure at 290GHz. “This work demonstrates the possibility to implement an LNA-first receiver front-end operating at frequencies as high as 2/3(fmax) with a lower noise figure than can be achieved using the mixer-first approach,” said Singh.

The dissertation is ‘Radio receiver frontend ICs at the subTHz/THz frequency range in silicon‘ and can be read in full.

It is to be discussed on Zoom tomorrow (25 June 2004) noon Finland time – or at the Oulun Puhelin (L5, Linnanmaa campus) in person.