Europe to get 10nm and 7nm FD-SOI pilot line

A European pilot line for digital, analogue and RF ICs on 10nm and 7nm FD-SOI was announced today at French research lab CEA-Leti in Grenoble.

FAMES Kick-Off CEA-Leti

Called Fames Pilot Line, it will create manufacturing processes for OxRAM, FeRAM, MRAM and FeFETs embedded non-volatile memories; RF switches, filters and capacitors; integrated inductors for dc-dc converters; and both heterogeneous and sequential 3D integration.

“By integrating and combining a set of cutting-edge technologies, the Fames Pilot Line will open the door to disruptive system-on-chip architectures and provide smarter, greener and more efficient solutions for future chips,” said CEA-Leti CTO Jean-René Lèquepeys.


Fames Pilot Line mapAs well as CEA-Leti in the Fames Consortium, is Imec, the other great European semiconductor research lab, as well as: Fraunhofer Mikroelektronik (Germany), Tyndall (Ireland), VTT (Finland), Cezamat WUT (Poland), UCLouvain (Belgium), Silicon Austria Labs (Austria), SiNANO Institute (France), Grenoble INP-UGA (France) and the University of Granada (Spain).


“No less than 43 companies, from materials providers and equipment manufacturers to fabless companies, EDAs, IDMs, system houses and end-users have formally expressed their support for Fames,” according to CEA-Leti. “The pilot line will be accessible to all EU stakeholders: universities, RTOs, SMEs and industrial companies, and all like-minded countries through annual open calls and upon request, following a fair and non-discriminatory selection process.”

Funding will come from participating member states and ‘Chips JU’, the latter a EU body promoting advanced semiconductor manufacture in Europe.

“Chips JU aims to act as a catalyst and a model for further public and private collaborations in key areas,” explained its executive director Jari Kinaret. “This pilot line will advance essential semiconductor technologies and foster the collaboration between several European actors.”

As well as this FD-SOI pilot line, Chip JU is to fund a pilot line for 2nm and smaller IC making technology.

Websites: Fames Pilot Line   Chips JU

FD-SOI: fully-depleted silicon-on-insulator, a scalable low-parasitic capacitance (and therefore low-power)  IC technology.

Image: Fames kick-off meeting participants

 


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