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At this week’s RISC-V Summit in San Jose, California, Balajii Baktha, founder and CEO of Ventana Micro Systems, used his keynote to introduce the Veyron V1 family of RISC-V processors, available as chiplets and IP.
Veyron V1 provides single thread performance and targets data centres, automotive, 5G, AI and client applications. The single socket performance and RISC-V’s open and extensible architecture produces gains in workload efficiency through domain specific acceleration. According to Ventana, it will extend Moore’s law in anticipation of the increased demands data centres expect to meet energy consumption and thermal management levels for efficient operation.
The company offers a standards-based Veyron V1 compute chiplet and reference platform and claims that these can reduce time to market by up to two years and reduce development costs by up to 75%. The cores have an eight-wide, aggressive out-of-order pipeline, with 16 cores per cluster and a high core count multi-cluster scalability of up to 128 cores, with 48MB of shared L3 cache per cluster. It operates at 3.6GHz and has an I/O MMU (input/output memory management unit) and Advanced Interrupt Architecture (AAP) system IP, top-down performance tuning methodology and for security has side channel attack mitigation. The Veyron V1 is based on 5nm process technology and will be available in the second half of 2023. The development platform is available now.
Using a chiplet allows designers to introduce right-sized compute, IO and memory functions, while keeping an eye of costs. A software development kit is also available which includes software building blocks already proven on Ventana’s RISC-V platform.
Baktha said the Veyron V1 gave the company “a significant first mover advantage” by allowing users to differentiate using the low latency chiplets to introduce products “with significant reduction in development time and cost compared to the prevailing IP models”.
The RISC-V CPU core is part of what is believed to be the first compute chiplet solution with chiplets supplied by different companies. It also enables the integration of a flexible domain specific accelerator for hardware/software co-design.
