Renesas to use RISC-V cores in ASSPs

“Renesas and Andes share the same vision to welcome the era of RISC-V being the mainstream CPU instruction set architecture (ISA for SoCs,” says  Frankwell Lin, President of Andes, “it marks the arrival of the open-source RISC-V ISA as a mainstream computing engine.”

The delivery of Renesas’ pre-programmed ASSP devices based on the RISC-V core architecture, combined with specialized user interface tools to set the application programmable parameters, will provide customers with complete and optimized solutions.

This capability eliminates the initial RISC-V development and software investment barrier. In addition, an extensive network of regional Renesas partners with specialized expertise will provide cutting edge and sharply focused customer support.