French research lab CEA-Leti has reported stacking three 300mm wafers for improved CMOS image sensors, using hybrid wafer bonding and high-density through-silicon vias. The announcement was made in three papers at ECTC, the 2024 IEEE Electronic Components and Technology Conference in Colorado. 6μm hybrid bonding pad pitch, and TSVs are 1 x 10μm It is working towards a new generation ...
Nexperia has introduced 30V and 12V n-channel trench mosfets in 1mm packaging. In 1 x 0.6 x 0.2mm DSN1006: PMCB60XN 30V, 4A, 50mΩ (4.5Vg) PMCB60XNE 30V, 4A, 55mΩ (4.5Vg), 2.5kV HBM ESD protection “This gives them the lowest on-resistance per die area among similar 30V mosfets in the market,” claimed the company. In 0.96 x 0.96 x 0.24mm DSN1006 (SOT8007) ...
Nujira is extending its foundry agreement with TowerJazz to include production of the Cambridge firm’s NCT-L1300 Coolteq.L ET modulator chip for LTE handsets. Nujira is gearing up for volume production to support 4G smartphone shipments in 2014. The NCT-L1300 is fabricated in TowerJazz’s proven 0.18 micron RF CMOS technology. “Over the last year we’ve built an excellent relationship with TowerJazz; its processes offer us the ideal ...
STMicroelectronics and Infineon Technologies have joined up with 3-D packaging specialists STATS ChipPAC, to develop next-generation embedded Wafer-Level Ball Grid Array (eWLB) packaging technology. The three companies will jointly own the resulting IP.
MicroStencil expects to see its fine-pitch stencil printing technology being used for wafer-scale packaging by laptop builders in the next six to nine months
Georgia Tech has developed a CMOS-compatible way to add fluid cooling channels to chips without thermal interface problems
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