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Tag Archives: stack

ECTC: Triple wafer stacking for image sensors with embedded AI

Leti wafer stack for AI image sensor

French research lab CEA-Leti has reported stacking three 300mm wafers for improved CMOS image sensors, using hybrid wafer bonding and high-density through-silicon vias. The announcement was made in three papers at ECTC, the 2024 IEEE Electronic Components and Technology Conference in Colorado. 6μm hybrid bonding pad pitch, and TSVs are 1 x 10μm It is working towards a new generation ...

Leti makes CMOS at 500°C for 3D sequential chips

Leti-500C-pmos

CEA-Leti scientists have made FDSOI CMOS at 500°C, “while showing strong performance gains especially in p-type MOS logic devices”, according to the French lab, which has branded the process ‘CoolCube’. 500°C processing is important when trying to shrink die by building CMOS with p-channel mosfets above rather than next to their n-channel counterparts – called a ‘3D sequential’ structure. If too much ...

Green Hills adds Excelfore in-vehicle network stacks to Integrity RTOS

GreenHils-Excelfore stacks rtos

Green Hills Software to offer Excelfore’s in-vehicle network (IVN) stacks, integrated and optimised with Green Hills’ Integrity real-time operating system (RTOS) and its embedded TCP/IP v4/v6 networking stack. The combined software will support: Ethernet AVB/TSN Talker/Listener DoIP SOME/IP RTP/RTCP (including IEEE 1733) gPTP Slave/Bridging “Together, these solutions provide the security, safety, performance and protocol support required in the next generation of vehicle ...

Free software to get LoRa metro range IoT wireless up and running

Semtech-LoRa-Basic-MAC

Semtech has announced software building blocks to ease the development of devices with LoRa wireless links – LoRa is a low data rate wireless link with a range of over 10km. They are free, supported, open-source software and specification compliant – intended to implement the common functions that all developers of end devices, gateways or applications must implement, according to ...

Vertical NAND avoids scaling issues

Glen-Hawk-Vice-President-of-NAND-Solutions-at-Micron-Technology.jpg

The pressure to find an alternative mainstream non-volatile memory to NAND is now much less urgent following the development of vertical NAND structures which stack memory cells on top of eachother.

Imec scales flash below 20nm

Imec has successfully combined a HfAlO/Al2O3/HfAlO stack as an inter-gate dielectric with a Si/TiN hybrid floating gate in a planar NAND Flash structure, allowing further cell scaling.