EDA and IP

Design for manufacture, power and standards are key issues, according to top three CEOs

Standard for how IP is implemented in EDA tools is released by the Spirit Consortium

Intel's Pat Gelsinger says the progression of Moore's Law will fundamentally change the tools required to design chips

Multiple die in a package seen as solution to rising Asic costs

Programmable firm hopes to increase demand for hard wired versions of its FPGAs

Growth from increasing number of cores, a shortage of engineering capacity and increasing importance of FPGAs

Router optimises wire by wire

Mentor Graphics is bringing a C synthesis product to market that was previously available to select customers. Catapult C takes standard C or C++, with no extra instructions, classes or timing information, and produces Verilog or VHDL code for either an Asic or FPGA. “The source is purely functional, so the designer doesn’t care about the architecture,” said Thomas Bollaert, ...

Golden Gate focusing on EDA for low power chips

EDA firm manages one per cent growth over last year's quarter