Cambridge tool converts Verilog description into C

Tenison EDA said its VTOC tool will allow designers to make efficient C models of their hardware, speeding both the software writing and verification processes.

Lots of Web-based tools can do this, said Jeremy Bennett, chief executive of Tenison, but they can’t do the complete language or they are very inefficient.

An efficient Verilog to C converter could be useful to three groups of users, said Bennett: Asic and SoC developers; intellectual property houses; and SystemC users.

In the first case, software developers are forced to wait while the hardware is created. VTOC would allow software engineers to use C models of the developing hardware and start coding earlier.

This is a much cheaper option than using emulation, is faster than simulation and comes in a form with which software engineers are comfortable.

Secondly, IP houses need to provide C models of their designs in order for buyers to test and verify the hardware. Handcoding a C model can be time consuming and is prone to errors.

Finally, for firms starting to use SystemC, the tool enables legacy Verilog code to be reused in new designs.

VTOC is based on general purpose compiler technology developed from several years work by Cambridge University’s Dr David Greaves. In its present form can turn Verilog into C, C++ or even SystemC. It does a complete parallel to serial compilation, said Bennett.

However, it could do the reverse function, giving Tenison a viable way of taking algorithms in C directly to hardware. This is something the firm plans to do in the future.

VTOC has already been used by a number of firms and chip developers, including Virata. They’ve done a chip from end to end – it’s a very big comms chip, said Bennett.