CDNLive: Cadence speeds verification of fast interfaces

Cadence Design Systems has introduced design verification IP for three standard interfaces.

These are CoaXPress for high-speed imaging, HyperRAM high-speed memory and the JEDEC Universal Flash Storage (UFS) 3.0 specification.

The three tool sets will be used for IP and system-on-chip (SoC) design verification specifically for automotive devices.

The UFS 3.0 specification doubles the throughput bandwidth from 1333MB/s in UFS 2.1 to 2666MB/s in UFS3.0 and will be used in advanced automotive and mobile designs.

The UFS 3.0 Memory Model provides a full-stack, including support for MIPI Unified Protocol (UniProSM) 1.8 and MIPI M-PHYSM 4.1.

The CoaXPress interface standard provides high-speed serial communication over coaxial cable.

It will be used for automated acquisition and analysis of video and images, which is becoming more important as engineers develop autonomous driving applications.

It also can be used in other industrial and machine vision applications requiring transfer speeds up to 6.25Gbit/s.

HyperRAM is a high-performance 333MB/sec read performance memory based on the HyperBus interface.

The firm’s VIP offerings are part of its verification tool suite and are optimised for Xcelium Parallel Logic Simulation, along with supported third-party simulators.

Cadence will present details of the VIP tools at its CDNLive 2018 technology event in Munich next week (7-9 May).