EDA and IP

Nottingham-based SFN (Search for the Next) has characterised its novel transistor-based logic, and claims that it matches CMOS performance even when made in older fabs. It would “enable chip designers to produce ICs in older 180nm, and even one micron, geometry fabs with the equivalent performance of CMOS devices made in state-of-the-art plants”, according to the company. “For example, a ...

Siemens Digital Industries Software is to participate in the Rapid Assured Microelectronics Prototypes (RAMP) Phase II initiative. RAMP is a programme established by the US Department of Defense (DoD) to develop secure design and prototyping capabilities to demonstrate how the DoD can securely leverage state-of-the-art microelectronics technologies without depending on a closed-security architecture fabrication process or facility. In 2020, the ...

Easy-PC has acquired IPC-2581 export capability along with other improvements with the introduction of version 26, according to Number One Systems, which develops the PCB design tool. IPC-2581 is a standard for PCB manufacturing and assembly data transfer which goes beyond Gerber files and adds information such as stack-up, nets and components. “As IPC-2581 has become a more common and ...

Agile Analog has announced a major recruitment drive to support its process-agnostic, analogue IP. The company aims to recruit engineers to significantly increase its IP portfolio and customer engagements. Hybrid working allows experienced analogue engineers to work from anywhere, but the company also recognises the importance of having collaborative in person spaces to support the successful growth of high performing ...

Imagination Technologies has announced its first real-time embedded RISC-V CPU. Called IMG RTXM-2200, the 32bit core is aimed at SoCs for networking, packet management, storage controllers, sensor management for AI cameras and smart metering, according to the company, which has revealed little more. Up to 128kbyte tightly coupled memory (instruction and data) can be provide for deterministic response, and Level ...

Siemens Digital has introduced Symphony Pro to extend Symphony’s mixed-signal verification capabilities to support new and advanced Accellera standardised verification methodologies with a visual debug cockpit with claimed productivity improvements of up to 10x. Automotive, imaging, IoT, 5G, computing and storage applications are driving strong demand for greater analogue and mixed-signal content in SoCs. Mixed-signal circuits are increasingly ubiquitous — ...

Kudelski IoT has announced a secure enclave intellectual property portfolio for integration into system ICs. When integrated, it is capable of “enabling compliance with most common industry security standards including NIST, FIPS, PSA and SESIP Level 3”, according to the company. Resulting hardware will be able to protect and manage keys, according to the company, providing SoC master secret key, ...

Cambridge-based Agile Analog has announced RC oscillator intellectual property for IC designers. Called ‘agileOSC RC’, it “is based on a traditional architecture which allows the frequency to be trimmed to remove the effects of process variation,” according to the company. It can also be configured as a free running clock where a high accuracy clock is not required. Start-up is typically ...

Agile Analog has added a voltage sensor to its portfolio of intellectual property, for IC designers that need to monitor fluctuations on on-chip power rails. Called ‘agileIR Drop’, despite its name, it does not monitor the voltage difference from end-to-end of a conductor. Instead the IP block provides real time monitoring of voltages at single points on rails to detect ...

RISC-V simulation company Imperas Software has announced a partnership with Breker Verification Systems, a provider of test content synthesis for verification environments, to develop interfaces and standards to unify functional verification design flows. “RISC-V represents an inflection point for semiconductor verification as the design freedoms provided by the open instruction set architecture means an assumption of the responsibility of the ...