It enables designers to perform closure directly at the top level. This is significant for AI, as well as space and defence projects, which rely on low latency, explained Yoan Dupret, Menta’s managing director and CEO.
Since 2013, Menta’s technology has been available as hard IP cores on any standard cell technology. The soft IP eFPGA allows customers to integrate eFPGA as they would any other digital IP. It can be mapped by the end user to any foundry on any standard cell technology node, says the company, enabling customers to do the physical implementation in their own environment with their own EDA tool flow. Users can choose the number and type of memories, DSPs and blocks, said Dupret, offering SoC and ASIC designers more flexibility and control of the IP implementation. It also contributes to lower costs, and the use of an asymmetric algorithm can reduce power consumption by a factor of four,” added Dupret.
eFPGA IP allows hardware to be reconfigured after manufacturing, allowing developers to upgrade and extend life cycles. The eFPGA IP acts as “design insurance” for SoCs and ASICs that include algorithms which are evolving faster than the chip manufacturing cycle, says the company.
Menta’s eFPGA technology is believed to be the industry’s only 100% standard-cell based solution. This allows engineers to rapidly port the eFPGA to any new process geometry required, even in industrial and rad-hard grade versions.
The nature of eFPGAs allows security protocols to be programmed after the manufacture, adding an extra layer of security. Menta’s standard cell based eFPGA technology is used to design secure, low cost, low power accelerators for AI, cryptography, and telecommunications algorithms.
The soft IP is available now.
Menta also offers Origami programming software to program its eFPGA in an intuitive FPGA tool environment. The software can be distributed to the SoC provider and their end customers. It also means that no new tool investment is required as the software can be supplied as an API.