Open standard for RISC-V verification is announced at DVCon

At this year’s (virtual) functional design and verification conference, DVCon US 2022, the RISC-V Verification Interface (RVVI) was announced by Imperas Software. The interface is available at github. The draft open standard defines “a number of interfaces required to bring together several of the subsystems required for RISC-V processor design verification”.

Components based on the open standard can be re-used across design teams and even across different companies, proposed Github. “In short, standards such as RVVI make re-use possible for RISC-V processor design verification.”

RVVI address the RTL of the core’s microarchitecture to provide tracing capabilities. The RVVI-VLG (Verilog interface) is defined in SystemVerilog and includes capabilities for use with cores with asynchronous iterrupts and debug modes.

Another area addressed by the standard is to verify a RISC-V core using a device under test against a reference model, encompassing all the architectural features and options including full asynchronous operation. The RVVI-API is a C/C++ API which can be used with C/C++ test benches and has a SystemVerilog DPI (deep packet inspection) wrapper for SystemVerilog test benches.

The third area addressed by RVVI is the reference model design verification subsystem. The RVVI-VPI covering timers, interrupts, debug, random event generators and printer/log/uart capabilities is still being developed.

According to Imperas, the RVVI can be adapted to any configuration permitted within the RISC-V specifications. In adopting the standard, developers can leverage all the common components off-the-shelf and explore additional options with third party verification IP.

SystemVerilog integration is compatible with Cadence, Siemens EDA and Synopsys tools and environments as well as Metrics cloud-based tools.