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Called iNoCulator, the “tool enables users to find the optimal NoC configuration, and the company believes that it is the fastest on the market”, it said. “This try-before-you-buy offer will enable engineers to see for themselves just how easy it is to design a NoC with our tool.”
Different configurations of the SoC architecture to be simulated for throughput and latency, and after power, performance, area and timing targets are set, the tool creates possible topologies that can be tweaked to find the optimal solution, said SignatureIP.
It supports non-coherent NoCs and can be configured as ring, mesh, concentrated mesh or torus topologies.
AXI, AHB, APB and SRAM interface protocols are supported, as are multiple bus widths, and connections to on-chip IP blocks such as PCIe, CXL and AI acceleration.
Multiple clocking schemes include GALS are handled, and it has powerisland generation and UPF (unified power format) output. “It creates a layered, scalable physically-aware network,” is the claim.
RTL generation can be aimed at an SoC design flow, or to an FPGA emulation flow.
An annual subscription license allows architectural exploration of any number of designs. “It provides access to all aspects of the tool and enables downloading the RTL of the final design for a fee per design download,” said SignatureIP.
