Circuit design

The executive director of R&D in Synopsys’ EDA group, Sashi Obilisetty, was presented with the Marie R. Pistilli Women in Engineering Achievement Award at this year’s DAC in San Francisco, California. The award recognises individuals who have “significantly helped advance women in electronic design”. This year’s recipient is an entrepreneur, founding DualSoft in 1998, focusing on RT analysis, which was ...

Joe Sawicki , executive vice president, IC EDA at Siemens, challenged the mutterings that Moore’s law has run its course, and said the semiconductor industry was blighted with pessimism. At this year’s DAC (Design Automation Conference) he set about looking at the figures in a new light. “There have been morose expectations and miserable prognostics, for like 20 years,” he reasoned, ...

The Texas Instruments MSP430 is practically synonymous with low-power processors and, although the company may not care much for the idea of clones of the architecture appearing, that is being helped by a crop of research processors that explore the limits of the threshold voltage of CMOS transistors. These designs are helping to push the MSP430 into lower-power territory than ...

Yoichi Yano, executive vice president of Renesas Electronics made energy saving the theme of his keynote at this week’s International Solid State Circuits Conference, describing some of the techniques the company is putting into action to make silicon suitable for self-powered sensor nodes.

The International Solid State Circuits Conference kicks off next week and Texas Instruments, which unveiled a low-energy digital signal processor last year based on near-threshold logic circuitry, is keen to tout its involvement in more low-power work this year.

Magnetic memory (MRAM) was not at my list of candidates for future cache memories but in a paper for the latest issue of IEEE Transactions on VLSI Systems, a group of engineers from Xi’an Jiaotong University make the case for using the memory to replace SRAM in level-one (L1) caches despite a very obvious drawback: the write speed and power ...

When looking at new architectures for low-power operation, it is easy to get fixated on one part of the design and ignore the ramifications for the rest of the system. The consequences of that are demonstrated in a paper that was presented at last year’s International Symposium on Low-Power Electronic Design in Japan. Rami Abdallah, Pradeep Shenoy, Naresh Shanbhag and ...

Field-programmable gate arrays (FPGAs) are notorious for high power consumption. They are hard to power down in the same way as custom logic – so they have considerable static power consumption – and they use a lot more gates to achieve the same job with their greater flexibility. However, a good proportion of an FPGA’s power consumption is avoidable. A ...

In an opinion piece for Electronics Weekly, head of Nujira Tim Haynes writes that the launch of LTE has met with some power problems. As such, it has not been all that different to that of 3G some ten years. Then as now, power was a major concern as handset designers had not optimised their products and were also waiting ...

In an invited paper for the International Electron Device Meeting (IEDM) in Washington DC this week, Dennis Buss of Texas Instruments talked about his experience in developing ultra-low power systems, something that he has been specialising in for the past few years.