Open Source Engineering

Microchip has a GUI development toolkit for 32bit SAMA5 and SAM9 series of Arm Cortex-A5 and ARM926EJ-S MPUs running Linux Called Ensemble Graphics Toolkit, it is a no-cost and royalty-fre open-source C++ suite based on the permissive Apache 2.0 open-source license. It works with the company’s chips, system-in-package and system-on-module products. “By taking advantage of underlying hardware acceleration, including graphics controllers ...

A reader-friendly guide to the recently-announced open-source hardware specification DIN Spec 3105 has been published, written on behalf of the Journal of Open Hardware by Jérémy Bonvoisin of the University of Bath, one of the many contributors to the specification in which German standards organisation Deutsches Institut für Normung solidly defines what ‘open-source hardware’ is, and what isn’t. The guide introduces the open-source hardware ...

German national standards body DIN (Deutsche Institut für Normung) has defined exactly what ‘open-source hardware’ is, and what it isn’t. This should mean an end to ‘open-washing’ – marketing partially or completely closed-source hardware as ‘open-source’. The definition is laid down in document ‘DIN Spec 3105 Open source hardware’, which has been written in English. Its creation builds on ‘Open ...

The University of Bath has designed an open-source medical-grade microscope that can be made for as little as £15 in its most basic form Called OpenFlexure microscope, “it is unique among 3D-printed microscope in its ability to yield high-quality images,” according to the university.” It has been designed to be easy to use, with an intuitive software interface and simplified ...

Taiwanese IP provider Andes Technology is offering RISC-V cores, acceleration hardware and development tools. Amongst planned cores is a free one. “With ‘Fast start’ into Risc-V, we will not only introduce our free starter, commercial grade core but also show which other options available, ranging from an ultra-low power MCU over a low power medium-sized Core up to Linux-capable multi-core processors ...

GAP 8 is an ultra-low-power Risc-V AI processor from Grenoble-based GreenWaves, aimed at inferencing (executing already-trained neural networks) inside battery-operated IoT sensors. “Battery-operated sensors have, until now, been restricted to simple data sources such as temperature and humidity,” according to the firm. “But there is increasing interest in processing richer data sources such as images, sounds, and vibrations. These applications require ...

Microchip detailed an FPGA family with a quad core 64bit RISC-V processor alongside the programmable array. Called ‘PolarFire SoC’, the “architecture brings real-time deterministic asymmetric multiprocessing capability to Linux platforms in a multi-core coherent CPU cluster”, according to the firm, which worked with Risc-V specialist SiFive to create the devices. Real-time operation is included for safety-critical, system control and trusted ...

Arrow has introduced a develoment board for ST Microelectronics’ new Linux-enabled MCU that combines a 209MHz Arm Cortex-M4 core for real-time processing with dual 650MHz Cortex-A7 cores for the open-source operating system to run a human-machine interface. Called Avenger96 Development Platform and System on Module (SoM), the parts are intended to work within the 96Boards ecosystems. “The SoM, based on ...

Now there is no need for a taxi driver taking the longest route and bumping up the fare, as even passengers talking in a foreign language can make themselves understood, with the in-vehicle translator developed by Luxoft with Ford. The system is powered by a SmartDevice Link enabled in-vehicle infotainment system. SmartDeviceLink technology is based on Ford’s Sync AppLink open ...

Researchers at Princeton University have discovered errors in the RISC-V instruction specification, leading to changes in the architecture, soon to be released. They were testing a technique created for analysing memory use, and found over 100 errors involving incorrect orderings in the storage and retrieval of information from memory in variations of the RISC-V processor architecture. RISC-V foundation replies to ...