Synopsys certifies AI design flows on Samsung 2nm

Synopsys says its AI-driven digital design and analogue design flows have achieved certification on Samsung Foundry’s SF2 process with multiple test chip tapeouts.

The reference flows, powered by the Synopsys.ai full-stack EDA suite, enhance PPA, boost productivity, and accelerate analog design migration for Samsung Foundry’s latest Gate-All-Around (GAA) process technologies.

The Samsung SF2 process was optimised using Synopsys’ AI-driven design technology co-optimisation (DTCO) solution which is said to deliver superior performance, power, and area (PPA) for the process compared to optimisation without the use of AI. Building on this success, the same co-optimisation techniques will be applied for Samsung’s advanced SF1.4 process.

“Achieving certification and multiple successful tapeouts of our digital and analogue flows, powered by Synopsys.ai, on the SF2 process, combined with proven Synopsys IP provides designers with a trusted path to meeting their aggressive design goals for a faster time to market,” says Synopsys vp Sanjay Bali.

“Working together we validated our PPA results using Synopsys’ certified digital flow, achieving 12% higher performance, 25% reduction in power, and 5% area reduction compared to the base design,” says Samsung vp Sangyun Kim.

Synopsys and Samsung are closely collaborating on AI-driven flows, including Synopsys DSO.ai for design productivity and PPA optimisation, and Synopsys ASO.ai for faster analog design migration.

This collaboration has resulted in a new analogue design migration reference flow using Synopsys ASO.ai for Samsung’s FinFET to GAA processes, enabling designers to efficiently migrate Samsung 8nm analogue IPs to SF2 process, adding to Synopsys’
established flows on Samsung’s 14nm to 8nm/SF5

Synopsys’ new design techniques include backside routing, local layout effect-aware methodology, and nanosheet cell design, to help customers meet their design goals for power, performance, and area on Samsung SF2 process family.

In addition, integrating backside routing and the super-cell approach using Synopsys’ digital implementation and signoff tools enables designers to increase transistor performance efficiency and density, optimise power consumption, and reduce area by up to 20% for Samsung’s SF2Z process technology compared to chips without backside routing capabilities.

Synopsys IP for Samsung standard and automotive processes from SF2 to SF14LPU delivers a competitive edge for chipmakers looking to reduce integration risk and accelerate time to silicon success for automotive, mobile, high-performance computing (HPC) and multi-die designs.

The standards-compliant, silicon-proven interface IP for advanced Samsung processes, include PCIe 6.0/5.0/4.0, DDR5, LPDDR5X/5/4X, MIPI M-PHY G5, eUSB2, USB 3.2/3.1, and DisplayPort which enable wide interoperability for commonly used
protocols.

To accelerate integration of chiplets in multi-die packages, Synopsys UCIe IP has taped out in SF2 and SF4x, and achieved silicon success in SF5A process technologies, to deliver robust die-to-die connectivity with low power and low latency.

Synopsys Foundation IP, including embedded memories, logic libraries and GPIOs, is also proven in silicon to deliver leading power, performance, and area in a range of Samsung process technologies.

Synopsys and Samsung are collaborating to deliver a broad range of IP for Samsung’s advanced process technologies.

Mutual customers can accelerate the development of multi-die designs using Synopsys 3DIC Compiler, a unified exploration-to-signoff platform for 2.5D and 3D heterogeneous integration and advanced packaging.

Qualified for Samsung Foundry’s SF2 process, Synopsys 3DIC Compiler supports Samsung’s advanced silicon processes, packaging technologies, and 3DCODE standard.

Synopsys is an active member of the Samsung Foundries’ MDI Alliance, helping mutual customers achieve a successful transition to 2.5D and 3D advanced packaging designs.