Avnet ASIC providing design services for TSMC 4nm and below processes

The services include recharacterizing standard cells for lower voltages, performing early RTL exploration to optimize power, performance, and area (PPA) tradeoffs, implementing an optimized clock tree, and utilizing transistor-level simulations to enhance the power optimization process.

The Avnet ASIC team built a full-scale technical A-Z approach to enable PPA optimization of high-performance chips working at extremely low voltage and proved it in TSMC’s 4nm process. Performance, dynamic and leakage power estimations have been confirmed by post-silicon validation.

The customer defined the board solution and chip implementation concept, requirements, and executed front-end design based on library characterization for near-threshold voltage operation. Avnet ASIC then executed this design to meet aggressive market targets, enabling the ultra-low-power performance of the customer’s application.

“One of the industry challenges today is to optimize application performance by choosing the correct technology to meet customer needs,” says Avnet’s Pavel Vilk.

The new services  follow on the February appointment  of the Avnet ASIC team to be a Value Chain Aggregator (VCA) by TSMC.

The appointment positions the Avnet ASIC team as a channel for TSMC ASIC customers, offering a full turnkey solution from design inception to layout and mass production, implemented in TSMC’s most advanced silicon processes.

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